Xing Huang

Biography

Dr. Huang received his doctorate degree in science from the Central China Normal University. His doctoral thesis focused on the design and implementation of radiation-hard high-speed optical transceiver ASICs in high-energy physics detector readout systems. During the completion of his thesis, He became increasingly interested in the design and verification of analog and digital ASICs for the application of high-energy experimental physics. He has experience in key building block design for precision time measurement ASIC, including phase shifter, precision clock distribution, ADC, PLL, serializer, high-speed line, VCSEL driver, charge pump, etc. He has experience in design in multiple CMOS processes. He joined the group of Professor Claudio Campagnari in 2022, and participated in the development of the electronics for the Endcap Timing Detector of the CMS experiment, with particular emphasis on the front-end integrating circuit. He is working remotely outside of the UCSB campus.

Research

All detectors on the LHC are undergoing upgrades to meet the demands of the HL-LHC operation to achieve the physics goals. One novel detector concept is officially chosen for both the CMS and ATLAS experiments to measure the arrival time of charged particles with a resolution of 30–40 ps per track at the start of the HL-LHC and 60 ps in the worst case at the end of the operation. In CMS, this is the minimum-ionizing-particle timing detector (MTD). The MTD has two parts: the barrel timing layer (BTL) and the endcap timing layer (ETL). In the ETL, the low-gain avalanche detector (LGAD) is read out using an Application-Specific Integrated Circuit (ASIC) called the endcap timing read-out chip (ETROC). The ETL readout ASIC chip (ETROC) will be designed to handle a 16×16 pixel cell matrix, each pixel cell being 1.3×1.3 mm2 to match with the LGAD sensor pixel size. The power consumption of ETROC is constrained by the cooling system of ETL and should be within 1 W/chip. This means that, after excluding the common circuitry, the power consumption of each channel or pixel should be kept below 3 mW.

Selected Publications

• Huang, Xing, Datao Gong, Suen Hou, Guangming Huang, Chonghan Liu, Tiankuan Liu, Ming Qi et al. "A 10-Gb/s Driver/Receiver ASIC and Optical Modules for Particle Physics Experiments." IEEE Transactions on Nuclear Science 68, no. 8 (2021): 1998-2004.
• Huang, X., D. Gong, D. Guo, S. Hou, G. Huang, S. Kulis, C. Liu et al. "A novel quad-channel 10 Gbps CMOS VCSEL array driver with integrated charge pumps." Journal of Instrumentation 15, no. 12 (2020): T12004.
• X. Huang, D. Gong, Q. Sun, C. Chen, D. Guo, S. Hou et al. "A 4-Channel 10-Gbps/ch CMOS VCSEL Array Driver with on-chip Charge Pumps." In Topical Workshop on Electronics for Particle Physics, p. 48. 2019.
• Deng, B., X. Huang, H. Sun, C-P. Chao, S-W. Chen, D. Gong, S. Hou et al. "A 40 Gbps optical transceiver for particle physics experiments." Journal of Instrumentation 17, no. 05 (2022): C05005.
• Zhang, Wei, Hanhan Sun, Christopher Edwards, Datao Gong, Xing Huang, Chonghan Liu, Tiankuan Liu et al. "A low-power time-to-digital converter for the CMS Endcap Timing layer (ETL) Upgrade." IEEE Transactions on Nuclear Science 68, no. 8 (2021): 1984-1992.
• Sun, Hanhan, Q. Sun, S. Biereigel, R. Francisco, D. Gong, G. Huang, X. Huang et al. "A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip." Journal of Instrumentation 17, no. 03 (2022): C03038.
• Sun, Hanhan, X. Huang, C-P. Chao, S-W. Chen, B. Deng, D. Gong, S. Hou et al. "QTIA, a 2.5 or 10 Gbps 4-channel array optical receiver ASIC in a 65 nm CMOS technology." Journal of Instrumentation 17, no. 05 (2022): C05017.
• Huang, X., C. Liu, A. Deiana, B. Deng, D. Gong, L. Hasley, S. Hou et al. "A prototype optical link board with redundancy design for the ATLAS liquid argon calorimeter Phase-2 upgrade." Journal of Instrumentation 17, no. 05 (2022): C05007.
• Chen, C., D. Gong, D. Guo, G. Huang, X. Huang, S. Kulis, P. Leroux et al. "Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade." Journal of Instrumentation 15, no. 03 (2020): T03005.
• Chen, Chufeng, Datao Gong, Suen Hou, Guangming Huang, Xing Huang, Szymon Kulis, Paul Leroux et al. "1.28 and 5.12 Gbps multi-channel twinax cable receiver ASICs for the ATLAS Inner Tracker Pixel Detector upgrade." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 981 (2020): 164439.